Intel is sponsoring a free one-day in-depth training on the Xeon Phi Coprocessor to be held at Perseverance Hall (LBNL, Building 54) on March 27th, 2015 from 9:00am to 4:00pm. This training will provide software developers the foundation needed for modernizing their code to take advantage of parallel architectures found in both the Intel® Xeon® processor and the Intel® Xeon Phi™ coprocessor, both of which will be available later this year to campus researchers and their collaborators on the Berkeley Research Computing Savio cluster.
The trend in high performance computing at the national centers, such as NERSC and the Texas Advanced Computing Center, is towards the use of energy-efficient many-core architectures, such as those found in the Intel Phi coprocessor and the Nvidia GPU, that feature many more and smaller cores for highly parallelized applications. As these architectures become more prevalent, it will be important for users to start transitioning their computational workload to take advantage of these systems.
Lunch will be provided. For more information and registration, please go here. This event, hosted by the LBNL IT Division High Performance Computing Services Group, is open to all LBNL and UC Berkeley staff and faculty. Space is limited so please register early!